As the miniaturization and high integration of semiconductor devices progress, semiconductor devices having vertical MOS transistors whose footprints, i.e. occupying area, are reducible, compared to planar (horizontal) MOS transistors, are proposed (for instance, refer to Patent Documents 1 and 2).
A vertical MOS transistor comprises a silicon pillar, a gate electrode formed around a sidewall of the silicon pillar so as to surround the silicon pillar, and a source and a drain formed over the silicon pillar and at the foot of the silicon pillar. In the vertical MOS transistor, the sidewall of the silicon pillar is a channel region. Such a vertical transistor is called SGT (Surrounding Gate Transistor).
Further, a semiconductor device normally has an ESD (Electro Static Discharge) protection device for protecting an internal circuit therein from surge voltage caused by electrostatic discharge (for instance, refer to Patent Document 3). For instance, the ESD protection device is connected to an external terminal and functions so that surge voltage from the external terminal is not applied to the internal circuit by clamping operation.
[Patent Document 1]
    Japanese Patent Kokai Publication No. JP-P2009-65024A, which corresponds to US2009/065856A1[Patent Document 2]    Japanese Patent Kokai Publication No. JP-P2009-81389A, which corresponds to US2009/085102A1[Patent Document 3]    Japanese Patent Kokai Publication No. JP-P2009-283690A